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Some notable changes come to RISC-V, x86, ARM64 with the new QEMU 10.0 update.
QEMU has significantly updated its ISC (Instruction set architectures) with many important updates.
This specific update focuses more on boosting the functionality for the next-generation emulation specifically for RISC-V, x86 and ARM64 ISAs.
For starters, RISC-V adopters will be happy to know the added support for newer chips and more feature enablements.
QEMU will be adding support for the Tenstorrent Ascalon CPU and RV64 Xiangshan Nanhu CPU.
In addition to that, if you are into AMD SoCs, the developers are also adding support for the Microblaze V generic board, and as it is designed to be highly modular with a configurable architecture suitable for embedded systems applications. It will be favorable for the developers to leverage the open-source RISC-V software ecosystem for easily.
Key additions include support for the RISC-V IOMMU system device, which allows for hardware-accelerated I/O operations with better security isolation. The release also introduces the svukte ISA extension and adds support for the ssstateen extension, expanding QEMU's capabilities for modern RISC-V implementations.
Enhancements in performance are evident through lower overhead for RISC-V vector unit-stride load and store operations, leading to greater efficiency in vector processing. Meanwhile, security receives an upgrade with the addition of SHA algorithm support and refined Pointer Masking functionality, now aligned with the Zjpm v1.0 standard.
The release also introduces support for the RISC-V Counter delegation ISA extension and ensures compatibility with both Smdbltrp and Ssdbltrp extensions. Additionally, the IOMMU page table cache has been enhanced with a new translation tag to boost performance.
There are some additional changes that include:
The changelog has more technical information if you are up for a longer read.
Since it has already been released, you find the latest version on the official download page to get the latest version.
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